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INTEGRATED CIRCUITS
DATA SHEET
74ALVC573 Octal D-type transparent latch; 3-state
Product specification Supersedes data of 2002 Mar 01 2003 Jun 25
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES * Wide supply voltage range from 1.65 to 3.6 V * Complies with JEDEC standards: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). * 3.6 V tolerant inputs and outputs * CMOS low power consumption * Direct interface with TTL levels (2.7 to 3.6 V) * Power-down mode * Latch-up performance exceeds 250 mA * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74ALVC573 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C. SYMBOL tPHL/tPLH PARAMETER propagation delay input Dn to output Qn CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k
74ALVC573
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74ALVC573 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74ALVC573 is functionally identical to the 74ALVC373, but the has a different pin arrangement.
TYPICAL 2.5 ns ns ns ns
UNIT
VCC = 2.5 V; CL = 30 pF; RL = 500 2.0 VCC = 2.7 V; CL = 50 pF; RL = 500 2.3 VCC = 3.3 V; CL = 50 pF; RL = 500 2.2 CI CPD input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes and 1 outputs enabled outputs disabled Notes CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 1. The condition is VI = GND to VCC. 37 7 3.5
pF pF pF
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE See note 1 INPUT OPERATING MODES OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; a) h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; b) L = LOW voltage level; c) l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; d) Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER 74ALVC573D 74ALVC573PW 74ALVC573BQ PINNING PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL OE D0 D1 D2 D3 D4 D5 D6 D7 GND DESCRIPTION output enable input (active LOW) data input data input data input data input data input data input data input data input ground (0 V) TEMPERATURE RANGE -40 to +85 C -40 to +85 C -40 to +85 C PINS 20 20 20 PACKAGE SO20 TSSOP20 DHVQFN20 L L L L H H LE H H L L L L Dn L H l h l h
74ALVC573
INTERNAL LATCH L H L H L H
OUTPUT Qn L H L H Z Z
MATERIAL plastic plastic plastic
CODE SOT163-1 SOT360-1 SOT764-1
PIN 11 12 13 14 15 16 17 18 19 20
SYMBOL LE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC
DESCRIPTION latch enable input (active HIGH) 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output supply voltage
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
handbook, halfpage
OE 1
VCC 20 19 18 17 16 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0
handbook, halfpage
2 3 4 5
OE 1 D0 2 D1 3 D2 4 D3 5
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3
D1 D2 D3 D4
GND(1)
6 7 8 9 10 Top view GND 11 LE
MNA979
573
D4 6 D5 7 D6 8 D7 9 GND 10
MNA806
15 14 13 12
15 Q4 14 Q5 13 Q6 12 Q7 11 LE D5 D6 D7
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO20 and TSSOP20.
Fig.2 Pin configuration DHVQFN20.
handbook, halfpage handbook, halfpage
11 1
C1 EN1
1 2 3 4 5 6 7 8 9 OE D0 D1 D2 D3 D4 D5 D6 D7 LE 11
MNA807
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12 5 6 7 8 9
MNA808
2 3 4
1D
19 18 17 16 15 14 13 12
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
handbook, halfpage
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3-STATE OUTPUTS
Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 D LE LE LE Q
MNA692
handbook, halfpage
LE
11 LE 1 OE
MNA809
Fig.5 Function diagram.
Fig.6 Logic diagram (one latch).
D0
D1
D2
D3
D4
D5
D6
D7
handbook, full pagewidth
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LE OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA810
Fig.7 Logic diagram.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage CONDITIONS 0 VCC = 1.65 to 3.6 V; enable mode 0 VCC = 1.65 to 3.6 V; disable mode 0 VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 3.6 V 0 -40 0 0 MIN. 1.65
74ALVC573
MAX. 3.6 3.6 VCC 3.6 3.6 +85 20 10 V V V V V
UNIT
C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO PARAMETER supply voltage input diode current input voltage output diode current output voltage VO > VCC or VO < 0 enable mode; notes 1 and 2 disable mode Power-down mode; note 2 IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. 3. For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. a) For TSSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. b) For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 to +85 C; note 3 VO = 0 to VCC VI < 0 CONDITIONS - -0.5 - -0.5 -0.5 -0.5 - - -65 - MIN. -0.5 MAX. +4.6 -50 +4.6 50 +4.6 +4.6 50 100 +150 500 V mA V mA V V mA mA C mW UNIT
VCC + 0.5 V
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 6 mA IO = 12 mA IO = 18 mA IO = 12 mA IO = 18 mA IO = 24 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -6 mA IO = -12 mA IO = -18 mA IO = -12 mA IO = -18 mA IO = -24 mA ILI IOZ input leakage current 3-state output OFF-state current power OFF leakage current quiescent supply current additional quiescent supply current per input pin VI = 3.6 V or GND VI = VIH or VIL; VO = 3.6 V or GND; note 2 VI or VO = 0 to 3.6 V VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 3.6 1.65 to 3.6 VCC - 0.2 1.25 1.8 1.7 2.2 2.4 2.2 - - - - - - - - - 0.1 0.1 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 - - - - - - - - - - - - - - 0.65 x VCC - 1.7 2 - - - - - - - - VCC (V) MIN. TYP.(1)
74ALVC573
MAX.
UNIT
- - - 0.7 0.8 0.2 0.3 0.4 0.6 0.4 0.4 0.55 - - - - - - - 5 10
V V V V V V V V V V V V V V V V V V V A A
0.35 x VCC V
Ioff ICC ICC
0.0 3.6 3.0 to 3.6
- - -
0.1 0.2 5
10 10 750
A A A
Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. For transceivers, the parameter IOZ includes the input leakage current.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
AC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C; see note 1 tPHL/tPLH propagation delay Dn to Qn see Figs 8 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPHL/tPLH propagation delay LE to Qn see Figs 9 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time OE to Qn see Figs 10 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time OE to Qn see Figs 10 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tW LE pulse with HIGH see Figs 9 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tsu set-up time Dn to LE see Figs 11 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 th hold time Dn to LE see Figs 11 and 12 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Note 1. All typical values are measured at Tamb = 25 C. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 3.8 3.3 3.3 3.3 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.7 2.5 2.0 2.3 2.2 2.8 2.1 2.4 2.3 3.0 2.4 3.0 2.3 3.4 2.2 2.8 2.7 - - - - - - - - - - - - VCC (V) MIN. TYP.
74ALVC573
MAX.
UNIT
5.4 3.5 3.6 3.3 6.0 3.8 3.7 3.3 6.4 4.5 4.6 4.0 7.0 4.4 4.4 4.4 - - - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
AC WAVEFORMS
74ALVC573
handbook, halfpage
VI VM
Dn input GND
tPHL VOH Qn output VOL VM
tPLH
MNA811
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VI VCC VCC 2.7 V 2.7 V tr = tf VM 2.0 ns 0.5 x VCC 2.0 ns 0.5 x VCC 2.5 ns 2.5 ns 1.5 V 1.5 V
Fig.8 Input Dn to output Qn propagation delay times.
handbook, full pagewidth
1/fmax VI LE input GND tW t PHL VOH Qn output VOL VM
MNA812
VM
t PLH
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V VI VCC VCC 2.7 V 2.7 V tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns
Fig.9 Latch Enable (LE) input pulse width and latch enable input to output (Qn) propagation delays.
2003 Jun 25
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
handbook, full pagewidth
VI OE input GND t PLZ VCC Qn output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH Qn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
MNA813
VM
t PZL
VM VX t PZH VY VM
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VI VCC VCC 2.7 V 2.7 V tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.15 V VOH - 0.3 V VOH - 0.3 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.10 3-state enable and disable times.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
handbook, full pagewidth
VI Dn input GND th t su VI LE input GND VM
MNA814
VM
th t su
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V VCC VCC 2.7 V 2.7 V VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.11 Data set-up and hold times for Dn input to LE input.
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V
Definitions for test circuit:
VI VCC VCC 2.7 V 2.7 V
CL 30 pF 30 pF 50 pF 50 pF
RL 1 k 500 500 500
VEXT tPLH/tPHL open open open open tPZH/tPHZ GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V
RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Load circuitry for switching times.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm
74ALVC573
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.043 0.055 0.394 0.016 0.039
8 0o
o
ISSUE DATE 99-12-27 03-02-19
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 0o
o
2003 Jun 25
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74ALVC573
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 9 vMCAB wM C y1 C
C y
1 Eh 20
10 e 11
19 Dh 0
12 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2003 Jun 25
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Manual soldering
74ALVC573
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes not suitable not suitable(4)
74ALVC573
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(5)(6) recommended(7)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74ALVC573
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Jun 25
17
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
NOTES
74ALVC573
2003 Jun 25
18
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
NOTES
74ALVC573
2003 Jun 25
19
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp20
Date of release: 2003
Jun 25
Document order number:
9397 750 11268

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